Power-on detection (“POD”) circuits, sometimes also referred to as “power detect”, “power-on-reset”, “power enable”, or “voltage detect” circuits, generally provide a power-on signal that identifies when the voltage level of a power supply voltage source has attained a predetermined acceptable level. Such circuits are typically implemented in a semiconductor device to prevent malfunctions from occurring when a power supply voltage is applied to the semiconductor device. When the semiconductor device is operated before the power supply voltage reaches the suitable operational level, abnormal operations may occur that may cause device failure. Accordingly, a reset signal resets the semiconductor device if a power supply voltage has been applied but does not reached a predetermined voltage level. The reset signal is released after the power supply has reached the predetermined voltage level range.
FIG. 1 illustrates one example of a conventional POD circuit 100. As shown in FIG. 1, the POD circuit 100 includes an array of resistors 104, switches 112, 114, an inverter 118, and a comparator 102. The resistor array 104 includes resistors 106, 108, and 110 coupled in series between a voltage source VDD and ground. Switch 112 is coupled to node 118, which is disposed between resistors 106 and 108, and to node 122, which is coupled to an input of comparator 102. Switch 114 is also coupled to node 122 and to node 120, which is disposed between resistors 108 and 110. The opening and closing of switches 112 and 114 is controlled by the feedback from the output of the comparator 102. As shown in FIG. 1, switch 112 receives feedback directly from the output of comparator 102, and switch 114 receives feedback from comparator 102 through inverter 118, which is coupled to node 116 at the output of comparator 102.
Comparator 102 compares the voltage received at node 122 from either node 118 or 120 with the reference voltage, VREF. The comparator will output a logic “1” or a logic “0” depending on whether the voltage received from node 122 is greater than or less than the reference voltage. For example, the comparator may output a logic “0” if the reference voltage is greater than the voltage at node 122 and output a logic “1” if the reference voltage is less than the voltage at node 122. The output of comparator 102, RSN, is used as the power-on-reset signal.
FIG. 2 illustrates another example of a conventional POD circuit 200. As shown in FIG. 2, the POD circuit includes first and second comparators 202A, 202B (collectively referred to as “comparators 202”), an array of resistors 204, and logic circuitry 212. The resistor array 204 includes resistors 206, 208, 210 coupled in series between voltage source VDD and ground. Comparator 202A receives a bandgap voltage, VREF, as one input and a voltage from node 214 as a second input. Similarly, comparator 202B receives the reference voltage, VREF, as one input and a voltage from node 216 as a second input. The comparators 202 compare the voltages received from nodes 214 and 216 to the reference voltage, VREF, and outputs a logic “1” or a logic “0” based on the comparison. For example, if voltage received from node 214 is greater than the reference voltage, VREF, then comparator 202A may output a logic “1” and vice versa. Logic circuitry 214 typically includes a plurality of logic gates and receives the outputs from the comparators 202 as inputs. The logic circuitry 214 outputs a power-on-reset signal, RSN, based on the signals received from the comparators 204. However, each of the POD circuits 100, 200 is susceptible to generating an undesirable false power on or reset signal.
Accordingly, an improved POD circuit is desirable.